Semiconductor device technology is increasingly relying on specialty semiconductor substrates to improve the performance of the n-channel MOSFETs (nFETs) and p-channel MOSFETs (pFETs) in complementary metal oxide semiconductor (CMOS) circuits. For example, the strong dependence of carrier mobility on silicon surface orientation has led to increased interest in hybrid orientation Si substrates in which nFETs are formed in Si with a (100) surface orientation (the orientation in which electron mobility is higher) and pFETs are formed in Si with a (110) surface orientation (the orientation in which hole mobility is higher), as described by M. Yang, et al. in “High Performance CMOS Fabricated on Hybrid Substrate with Different Crystal Orientations,” IEDM 2003 Paper 18.7 and U.S. patent application Ser. No. 10/250,241, filed Jun. 17, 2003, now U.S. Pat. No. 7,329,923, entitled “High-performance CMOS SOI devices on hybrid crystal-oriented substrates.”
Amorphization/templated recrystallization (ATR) methods for fabricating hybrid orientation substrates such as those disclosed in U.S. patent application Ser. No. 10/725,850, supra, typically start with a first semiconductor layer having a first surface orientation directly bonded to a second semiconductor layer having a second surface orientation different from the first. Selected areas of the first semiconductor layer are amorphized by ion implantation, and then recrystallized into the orientation of the second semiconductor layer using the second semiconductor layer as a crystal template.
FIGS. 1A-1D show a “top amorphization/bottom templating” version of the ATR method of U.S. patent application Ser. No. 10/725,850, supra, for forming a bulk hybrid orientation Si substrate. In this version of ATR, the first semiconductor layer being amorphized is on the top and the second semiconductor layer acting as a template is on the bottom. Specifically, FIG. 1A shows the starting substrate 10 which comprises a top silicon layer 20 having a first surface orientation, a bottom silicon layer or substrate 30 having a second surface orientation different from the first, and a bonded interface 40 between them. FIG. 1B shows the substrate of FIG. 1A (designated now as 10′) after formation of dielectric-filled shallow trench isolation (STI) regions 50. Selected regions of top Si layer as 20′ are then subjected to amorphizing ion implant 60 to produce one or more amorphized regions 70, as shown in FIG. 1C. The amorphizing ion implant 60 would typically be performed with Si or Ge ions. Amorphized regions 70 span the entire thickness of the upper Si layer 20″, and extend into the lower Si layer 30′. The amorphized regions 70 are then recrystallized into the second surface orientation, using the lower Si layer 30′ as a template, to produce (idealized) planar hybrid orientation substrate 80 with recrystallized, changed-orientation Si region 90 as shown in FIG. 1D. In this example, the orientations of Si regions 30″ and 90 may have a (100) surface orientation, while the Si regions 20″ may have a (110) surface orientation.
It should be noted that the notation (jkl) indicates a family of crystal planes with Miller indices j, k, and l, and that the notation <j′k′l′> indicates a family of equivalent directions with Miller indices j′, k′, and l′. Here and in the remainder of this application, the “in-plane <j′k′l′> direction” of a crystal having a (jkl) surface orientation should be taken as referring to <j′k′l′> directions which are coplanar with the (jkl)-oriented crystal's surface.
In contrast to the idealized outcome shown in FIG. 1D, recrystallization of the amorphized Si region 70 in the structure of FIG. 1C more typically results in a structure like that of FIG. 2, where changed-orientation Si region 90 includes trench-edge defects 99. For the case in which changed-orientation Si region 90 has a (100) surface orientation and rectilinear sides aligned with the Si crystal's in-plane <110> directions, the trench-edge defects form a continuous band of defective Si 99, as shown in the top view of FIG. 3A. These trench-edge defects, associated with slow-growing (111) planes encountered during recrystallization, have been described by N. Burbure and K. S. Jones “The effect of oxide trenches on defect formation and evolution in ion-implanted silicon,” Mat. Res. Soc. Symp. Proc. 810 C4.19.1 (2004). These trench-edge defects are very stable and cannot be removed even by annealing at 1325 C for 5 hours.
As discussed in U.S. patent application Ser. No. 11/142,646, now U.S. Pat. No. 7,291,539, Si device regions with these trench-edge defects are not suitable for FETs whose geometry requires the FET's gate to cross over the trench-edge defects, as shown in FIG. 3B, where nFET 105 on the structure of FIG. 3A comprises gate 114 and source and drain regions 116 and 118. Defective edge regions 99 that pass directly under gate 114 provide a potentially low-resistance leakage path between the FET's source and drain regions.
As further described in U.S. patent application Ser. No. 11/142,646, now U.S. Pat. No. 7,291,539, ATR process sequences in which the STI patterning is performed after ATR may be used to avoid the trench-edge defect problem encountered with “ATR-after-STI” process sequences. While these “ATR-before-STI” alternatives still leave defective border regions between changed-orientation and original-orientation RX regions, the defective border regions can be removed and replaced by STI. However, this approach starts to become problematic when device scaling requires the original-orientation and changed-orientation Si regions to be separated by isolation regions narrower than the width of the defective border regions (usually about the thickness of the direct silicon bonded (DSB) layer being amorphized). In addition, the ATR-before-STI approach typically requires additional alignment steps, since the patterned amorphization and recrystallization does not leave anything to which the STI level could be aligned (in contrast to the ATR-after-STI approach in which the patterned ATR is easily aligned to the STI shapes).
The trench-edge defects described by Burbure and Jones supra are also seen in the source/drain (S/D) regions of FETs fabricated in (100)-oriented Si for cases in which the source/drain processing includes an amorphization and recrystallization step. (S/D amorphization is a preferred adjunct of the doping process because it improves dopant activation.) This is illustrated in FIGS. 4A-4H, where FIGS. 4A-4D are top view pictorial representations and FIGS. 4E-4F are cross section views through lines 4E-4E, 4F-4F, 4G-4G, and 4H-4H of FIGS. 4A-4D respectively. Rectilinear Si device region 140 having a (100) surface orientation and surrounded by STI 150 is first formed with the edge alignment and orientation shown in FIG. 4A (cross section view FIG. 4E). Gate 160 (or gate footprint 160′ in the top view figures) with underlying gate dielectric 161 is then formed on Si device region 140 (FIGS. 4B and 4F), followed by ion implantation (using gate 160 as a mask) to form amorphized and doped S/D regions 170 (FIGS. 4C and 4G). Recrystallized S/D regions 171 and trench-edge defects 180 resulting from the recrystallization/dopant activation anneal are shown in FIGS. 4D and 4H. Because the implant is performed using the gate as a mask, the trench-edge defects do not extend under the gate as they do for the blanket amorphization case of FIG. 3B. However, these defects are still a concern, especially when their dimensions staff approaching those of the source and drain.